
Introduction The heteroepitaxial growth of oxide materials on silicon(001) is of great interest in the semiconductor industry to replace traditional SiO2 based gate dielectric layers. Epitaxial oxides may also have novel applications such as oxide heterostructures and growth buffer layers. Our research objectives are to investigate whether CVD (chemical vapor deposition) or ALD (atomic layer deposition) techniques can achieve high quality SrTiO3 interfaces with silicon. Impressive results have previously been demonstrated with molecular beam epitaxy techniques (see Yang et. al. J. Mater Res., vol 17 (2002) page 204 for example), but CVD and ALD techniques are generally preferred over MBE methods for manufacturable processes in the semiconductor industry. However, whereas MBE uses elemental sources (Sr and Ti metal, for example) and submonolayer control of the element fluxes (in a ultra-high vacuum chamber), CVD and ALD techniques rely on a chemical reaction between a gaseous compound (a metal-organic such as Sr(tmhd)2, for example) and the growth surface. Thus, ALD and CVD have complicated chemical reactions that must be understood and controlled to achieve the desired growth results. Our research seeks to discover a reaction sequence that can achieve these objectives
Our Approach is to investigate the submonolayer chemical reactions of strontium compounds, beta-diketonate metal-organic ligands, and co-reactants such as oxygen and H2O with Si(001)-2x1 using ultra-high vacuum surface science techniques such as LEED, RHEED, STM, mass spectroscopy, and AES.
Introduction Molecular Electronics is a promising new field of nanotechnology where the goals are to invent electronic devices that use molecules to perform active functions such as switching, charge storage, or sensing, for example. Molecular electronics may one day replace or supplement silicon integrated circuit technology to advance computing beyond the capabilities of silicon technology. The idea holds great promise due to the inherent nanometer size of molecules and the wide range and complexity of molecules that can be synthesized. Presently, researchers are focussed on understanding the physics of electrical charge transport through molecules, so that one day devices can be designed. However, its not easy to measure the electrical properties of one molecule! Several techniques have been invented to perform such experiments; the techniques include scanning probe microscopy measurements, mechanical break junctions, advanced electron-beam lithography techniques, electrochemical narrowing, nanopore geometeries, and others. However, due to reproducibility problems, there is still a need for new concepts and inventions.
Most electronic molecules of present interest are organic and have overall lengths on the order of 1 to 3 nanometers. The molecules are engineered to have reactive head and tail groups such as thiol (-S-H) terminations. These head and tail groups are reactive with metal surfaces such as copper, palladium, silver, platinum, and gold; and they form strong bonds between the molecules and the surface. Measuring the electrical transport properties of these tiny molecules requires two electrodes with a separation of molecular size, ~1 to 3 nanometers. Patterning sufaces with such a small electrode separation is not generally possible, and alternative approaches are needed. Moreover, the availble data on electrical transport through molecules have discovered that the electrode structure and electrode-molecule binding greatly influences the observed electrical properties. Therefore, a nanoelectrode fabrication technique needs to have control of the electrode composition and structure in addtion to the electrode sepration.
Our Approach is to use advanced reaction engineering methods such as atomic layer deposition (ALD) to create reproducible and robust nanogap electrodes for measuring electronic molecules. ALD growth is a growth method where metal-organic compounds are used with co-reactants to grow thin films in a layer-by-layer method. Layer-by- layer growth refers to the method in which the films are grown not as a continuous process (such as chemical vapor deposition), but rather in a slow, sequential reaction process where co-reactants are exposed to the growth surface separately and the reactor is purged between reactants. A growth reaction might proceed as follows: flow reactant A, purge with inert gas, flow reactant B, purge with inert gas, repeat many times. The ALD approach only works with some reactant combinations, but when it does work one can grow films one layer at a time. Thus, the method gives very reproducible thickness control, something we can take advantage of for molecular electronics. Our method uses opposing electrodes that are initally separated by a (relatively) large gap of 50-100 nm. The inital gap can be easliy patterned by many exisiting techniques including UV lithography and electron beam lithography. The important step is to then grow the electrodes by ALD until the gap has the desired separation of 1-3 nm. The special characteristics of the ALD approach allow sub-monolayer control of the gap separation so that reproducible structures can be realized. The figure above demonstrates the use of our scanning probe microscope to measure the gap separation in our reactor without having to remove the samples from the reactor. We also use electron tunneling to measure the gap separation. In addition to the precise contorl over the nanogap-electrode structure, our method has a number of other advantages. In particular, we can anneal our nanostructures before, during, or after nanogap formation to alter the electrode nanostructure and optimize the elctrode properties for molecular devices. These nanostructures are then used to investigate the electrical properties of molecular devices.
Introduction Modern integrated circuits have over 100 million transistors on a piece of silicon about thumb size and 1 mm thick. These transistors act as switches to create logic states for computing, and each transistor needs source, drain, and gate connections. These connections are provided by tiny ( ~ 0.1-0.2 um wide wires that are embedded in a dielectric insulator layer. While the silicon transistors are confined to the surface plane of the silicon wafer, the wires are stacked (like a parking garage) in multiple levels to provide all the needed signals. Modern integrated circuits have approximately 10 layers of interconnect. Up until the late 1990's, these wires were made out of aluminum, but advanced integrated circuits are now made with copper metal using a fabrication scheme known as damascene processing. Copper has a lower resistivity than aluminum, and the reduced wire resistance leads to reduced signal delays and faster processor speeds. However, like other transition metals, copper poisons silicon and even trace amounts will damage the silicon devices. This is particularly important because copper is known to diffuse rapidly through silicon. Barrier layers are used to contain copper atoms and keep them from diffusing into the surrounding layers, and from poisoning the transistor devices. The challenge, however, is that future generations of interconnect require the barrier layers to be less than 10 nm thick, approaching 1 nm! Can a 1 nm barrier keep copper contained and avoid device failure over the life of the product?
Our Approach is to discover the mechanisms of copper transport in the dielectric layers in order to gain insight into how to design a barrier, and to determine the consequences if the barrier fails. For example, does copper diffuse as a neutral or as an ion, if the later, Cu+ or Cu++? How does the transport rate depend on temperature and applied voltages? How do the barrier microstructure, thickness, and other properties act to retard copper diffusion? How do we measure and quantify copper diffusion? Our research has provided some interesting insights into this problem. For example, using temperatures up to 300C and electric fiels up to 105 volts/cm, we did not observe any diffusion of copper metal into SiO2! These results are contrary to general perceptions of copper diffusion. The experiments showed that there was no observable diffuion of copper in Cu/dielectric/silicon MOS (metal-Oxide-Semiconductor) structures even at these quite severe conditions. However, copper diffusion was observed when the copper electrodes were exposed to oxygen. Oxidized copper electrodes lead to measurable copper diffusion at elevated temperatures and with applied voltages. We can measure and quantify the rates of reaction and transport with both electrical and chemical measurement techniques and we have built a transport model to explain the experimental data (see image above). Recently, we have discovered interesting results that suggest a kinetic mechanism for copper injection into the dielectric (manuscript in preparation...)
Introduction Recently, there has been much discussion about a hydrogen economy based on efficient hydrogen fuel cells for energy. However, there are a number of significant technical challenges to the widespread use of hydrogen fuel cells. Some of these include hydrogen generation, storage, and delivery. A subset of these challenges is the cost reduction of the materials that are used to make the hydrogen fuel cell. One of the significant costs is the use of precious metals (platinum) as the electrocatalyst. Platinum catalyzes the splitting of hydrogen into ions that diffuse across the proton exchange membrane (a thin membrane that allows hydrogen to diffuse across it, but prevents electrical charge transport). Hydrogen ions combine with oxygen at the cathode side of the membrane to make H2O, the product. As the hydrogen diffuses through the membrane, electrons travel through the external cicuit where they do work in a motor, for example. In addition to its cost, platinum also suffers from CO (carbon monoxide) poisoning. Even trace amounts of CO can chemisorb onto the active platinum sites and block the hydrogen reaction. Therefore, CO levels need to be kept low in the hydrogen feed stream, but this is difficult if the hydrogen is generated by an onboard reformer. A great advance could be made if an alternative material could be used as an electrocatalyst with increased CO tolerance.
One possible substitute for platinum is tungsten carbide. Tungsten carbides are known to have a chemical reactivity similar to the platinum group metals, and are cheaper and more CO tolerant. However, these materials have not demonstrated the catalytic activity sufficient to compete with platinum. Dr. Chen and his group (Chemical Engineering at UD) has investigated the carbides in great detail using well controlled ultra-high vacuum surface science experiments to investigate the elementary chemical reactions that occur on platinum and carbide surfaces. These experiments suggest that tungsten carbide does have promise as an electrocatalyst, but it is a challenge to connect UHV surface science results with practical electrocatalyst that can be fabricated and tested in electrochemical cells. In particular, the difficulty of controlling the stoichiometry and surface properties of tungsten carbides may have prevented the true potential of the materials from being measured previously.
Our Approach is to apply advanced reaction engineering methods based on chemical vapor deposition (CVD) and atomic layer deposition (ALD) to synthesized high quality WC materials that can be altered, tested, and investigated to understand the potential of these materials. The CVD of WC materials is challenging due to the high temperatures (> 1000C) necessary to activate the chemistries and to make WC materials. In addition to the challenge of forming the right material phase (WC vs. other tungsten carbide materials) carbon can cover the WC material and prevent the desired surface chemistry. ALD techniques are being investigated to develop a new process that can be used to make high quality materials for testing in fuel cells and other applications.